The present invention relates broadly to a process for defining semiconductor gates, and in particular to a CCD gate definition process.
In the prior art, the definition of lines with narrow spaces in between is a difficult process. Structures with narrow spaces in between lines occur in VHSIC and CCD type integrated circuits. In view of the great potential for process defects, the narrow spaces, in the order of 0.5 and 3.mu.m, are not properly defined in any of the areas wherein the conductive material is not removed from the spaces. There are two reasons that are attributed for this defect which are reticle problems, and/or defects in the photoresist. The reticle problems which comprise elements such as dust and/or defects in the gap regions, can be eliminated by double-stepping or careful reticle inspection. However, the defects which exist in the photoresist, such as bridging or webbing in between lines requires a process that is tolerant to the photoresist limitations, and also one that eliminates electrical shorts between lines.
The definition of geometrical patterns with fine shapes and gaps in integrated circuits is limited by the defects in the defining layer, e.g., the photoresist or a thin film that is patterned with a photoresist layer. Typically, the defects in the photoresist are reproduced in the etched pattern. In a positive resist process, the defects consist of photoresist regions in which the photoresist does not normally develop when exposed to light. If these regions are located between the conductive lines, electrical shorts occur. Similarly if such defects occur in any contact window areas incomplete contact window openings will occur. While the number of photoresist defects is small, nevertheless in VLSI circuits, the probability is considerable that a defect will will occur within a circuit.
Since the number of photoresist defects is small, a process technique can be employed to completely circumvent the effects of photoresist defects. A double masking process is very effective in reducing the effects of resist defects. The reduction of detects occurs because the probability is very small that a photoresist defect will occur in a the same place for two sucessive masking operations.
The state of the art for processes which define semiconductor structure such as CCD gates is well represented and alleviated to some degree by the prior arts methods and techniques which are contained in the following U.S. Patents:
U.S. Pat. No. 3,506,441 issued to Gottfried on April 14, 1970;
U.S. Pat. No. 3,823,015 issued to Fassett on July 9, 1974;
U.S. Pat. No. 4,352,870 issued to Howard et al on October 5, 1982.
In the prior art, the process of CCD gate definition in order to prevent or eliminate shorts between the gates of a CCD was not addressed to any great extent. U.S. Pat. No. 4,352,870 discloses a high resolution two-layer resist composition with a sensitive and thicker resist at the lower layer allowing for the production of lines on the order of 400 .ANG. (angstrom) in width separated by spaces on the order of 400 .ANG.. The Gottfried reference, U.S. Pat. No. 3,506,441 discloses a double photoresist processing method for producing printed circuit substrates having closely spaced, fine line circuitry devoid of pinholes. Any imperfection formed during the application of an initial layer of photosensitive material upon a circuit substrate, which would result in a pinhole upon exposure of the substrate to an etchant, is corrected by the application of an additional layer of photoresist. The Fassett reference, U.S. Pat. No. 3,823,015 discloses a photo-masking process in which a method of pattern definition employing photoresist masking techniques useful in photoengraving generally and in semiconductor processing specifically wherein defects due to inherent mask flaws are minimized and mask tolerance is improved including the steps of thrice defining and etching a pattern definition layer using separate photo masks or, where possible, by indexing the same photo mask whereby flaws in the masks do not coincide. The present invention is intended to satisfy that need.